A conventional CMOS reference voltage circuit is described in detail in the specification of Japanese Patent Kokai Publication No. JP-A-11-45125. In terms of obtaining a reference voltage by a current-to-voltage conversion, this reference voltage circuit naturally is the same as an earlier devised reference voltage circuit of this kind in which a temperature characteristic is cancelled out. However, in the earlier devised reference voltage circuit in which the temperature characteristic is cancelled out, a reference current having a positive temperature characteristic is converted to a voltage by a circuit comprising a resistor and a diode (or a diode-connected transistor), and the circuit obtains a voltage component in which the amount of voltage drop at the resistor has a positive temperature characteristic and a voltage component in which the forward voltage at the diode (or diode-connected transistor) has a negative temperature characteristic, and adds these temperature characteristics, thereby obtaining a reference voltage of about 1.2V in which the temperature characteristic has been cancelled out.
On the other hand, with the proposed reference voltage circuit described in the above-cited Japanese Patent Kokai Publication No. JP-A-11-45125, a reference current having almost no temperature characteristic is obtained, the current is converted to a voltage by an output circuit comprising only a resistor, and a reference voltage having any desired voltage value is obtained.
Accordingly, since 1.2V, from which the temperature characteristic has been cancelled out, stipulated as the output voltage of this conventional type of reference voltage circuit is obtained upon being converted to a current value within the circuit, the reference voltage circuit is outstanding in that in can be operated at a power-supply voltage of less than 1.2V.
In the textbook entitled “Analog Circuit Design Techniques for Applying CMOS to Mobile Wireless Terminals” (1999, published by Torikeppsu K.K.), the author of which is the present Inventor, a “Current-Mode-Type Reference Voltage Circuit” that was made public immediately within the same year is introduced and a detailed circuit analysis thereof is described.
In particular, in reference voltage circuits thus far, since use is made of a forward voltage of a diode (or diode-connected transistor) and this is a voltage component having a negative characteristic, a deviation from the temperature characteristic regarding the forward voltage of the diode (or diode-connected transistor) appears in the output voltage to a marked extent.
That is, although the forward voltage of the diode (or diode-connected transistor) possesses a negative temperature characteristic, the slope of the negative temperature characteristic becomes blunt as temperature falls.
On the other hand, a voltage having a positive characteristic is realized by obtaining a current, which flows into a resistor, owing to a difference voltage between forward voltages of two diodes (or diode-connected transistors) having different current densities, and converting this current to a voltage by the resistor.
In accordance with the content described in the patent document cited above, the operation thereof will be described. As shown in FIG. 7, a resistor R2 is divided into voltage-dividing resistors R2A and R2B and a divided voltage VB′ is output, and a resistor R4 is divided into voltage-dividing resistors R4A and R4B and a divided voltage VA′ is output. Furthermore, the common gate voltage of transistors P1 and P2 is controlled by an operational amplifier (an ordinary operational amplifier or a differential amplifying circuit) in such a manner that VA′=VB′ will hold.
Accordingly, we haveVA′=VB′  (1)
Further, currents I1, I2 that are output from p-channel MOS transistors P1, P2, respectively, are equal to each other.I1=I2   (2)
The current I1 is split into a current I1A that flows into a diode D1 and a current I1B that flows into a resistor R4 (=R4A+R4B). Similarly, the current I2 is split into a current I2A that flows into a serially connected resistor R1 and commonly into N-number of parallel-connected diodes D2, and a current I2B that flows into a resistor R2 (=R2A+R2B).
If we assume the following:R2=R4   (3)then Equations (4) and (5) below will hold.I1A=I2A   (4)I1B=I2B   (5)
Accordingly, we have the following:VA=VB   (6)
Further, if we assume that the forward voltages of diodes D1 and D2 are VF1 and VF2, respectively, then replacing, we have the following:.VA=VF1   (7)VB=VF2+ΔVF   (8)
From Equations (7) and (8), we have the following:ΔVF=VF1−VF2   (9)
The voltage drop across the resistor R1 is ΔVF, and the currents I2A and I1B are represented by Equations (10), (11), respectively, below.I2A=ΔVF/R1   (10)I1B=I2B=VF1/R2   (1)
Here the following holds:ΔVF=VT1n(N)   (12)where VT represents thermal voltage and is expressed byVT=kT/q   (13)where T represents absolute temperature [K], k the Boltzmann constant and q the unit electronic charge.
An output current 13 (=I2) of a p-channel MOS transistor P3 is converted to a voltage by a resistor R3, and an output voltage Vref is expressed by Equation (14) below.
                                                        Vref              =                              R                ⁢                                                                  ⁢                3                ×                13                                                                                        =                              R                ⁢                                                                  ⁢                3                ⁢                                  {                                                            VF                      ⁢                                                                                          ⁢                                              1                        /                        R                                            ⁢                                                                                          ⁢                      2                                        +                                                                                            [                                                      VT                            ⁢                                                                                                                  ⁢                            1                            ⁢                                                          n                              ⁡                                                              (                                N                                )                                                                                                              ]                                                /                        R                                            ⁢                                                                                          ⁢                      1                                                        }                                                                                                        =                                                (                                      R                    ⁢                                                                                  ⁢                                          3                      /                      R                                        ⁢                                                                                  ⁢                    2                                    )                                ⁢                                  {                                                            VF                      ⁢                                                                                          ⁢                      1                                        +                                                                  (                                                  R                          ⁢                                                                                                          ⁢                                                      2                            /                            R                                                    ⁢                                                                                                          ⁢                          1                                                )                                            ⁡                                              [                                                  VT                          ⁢                                                                                                          ⁢                          1                          ⁢                                                      n                            ⁡                                                          (                              N                              )                                                                                                      ]                                                                              }                                                                                        (        14        )            
In Equation (14), {VF1+(R2/R1)[VT1n(N)]} is a voltage value of about 1.205V from which the temperature characteristic has been cancelled. More specifically, VF1 has a negative temperature characteristic (temperature coefficient) of about −1.9 mV/° C., and VT has a positive temperature characteristic (temperature coefficient) of 0.0853 mV/° C. Accordingly, the temperature characteristic of the output voltage Vref is cancelled out, and therefore the value of (R2/R1)1n(N) is 22.27.
Further, since VT is 26 mV at an ambient temperature, (R2/R1)[VT1n(N)] is approximately 579 mV at an ambient temperature. Accordingly, if we assume that VF1 is 626 mV at an ambient temperature, then {VF1+(R2/R1)[VT1n(N)]} will be approximately 1.205V.
The temperature characteristic will now be discussed in detail. A resistor R4 is connected in parallel with the diode D1. If the temperature is low, therefore, the value of the current I1B that flows into the resistor R4 (=R4A+R4B) tends to decrease owing to the non-linearity of the temperature characteristic possessed by the diode. On the other hand, a resistor R1 is connected in series with the diode D2. If the current I2A that flows into the diode D2 has a positive temperature characteristic, therefore, then the voltage VB across the diode D2 and resistor R1 will fall below the voltage VA (=VF1) at the diode D1.
Owing to control by the operational amplifier DA1, the two voltages (the voltage VA at diode D1 and the voltage VB across diode D2 and resistor R1) become equal. With an increase in current (the current I2A that flows into the diode D2) at a low temperature, therefore, the two voltages become equal. At a high temperature, on the other hand, the action is the reverse.
That is, in the circuit shown in FIG. 7, the currents I1A and I2A that flow into the diodes D1 and D2, respectively, are set to a temperature characteristic that is lower than the temperature characteristic decided by [VT1n(N)]/R1, and the currents (VF1/R2, VF1/R4) that flow into the resistors R2 and R4, respectively, increase slightly at a low temperature.
Thus, since the drive currents I1, I2 and I3 that are supplied from the p-channel MOS transistors P1, P2 and P3 act in a direction that cancels out the non-linearity of the temperature characteristic exhibited by the forward voltage of the diodes, the temperature characteristic of the reference voltage obtained can also be set to a characteristic that is very near a straight line having little fluctuation with respect to temperature.
Further, since the ratio of the resistors (R3/R2) does not possess a temperature characteristic, the reference voltage Vref that is output also is a voltage from which the temperature characteristic has been cancelled out. Here the resistor ratio (R3/R2) can be set at will.
If I<(R3/R2) is set, the output voltage Vref becomes a voltage higher than 1.205 V, and if I>(R3/R2) is set, the output voltage Vref becomes a voltage lower than 1.205 V
In the above-cited patent document, N=10 is described as the specific value of N. When the circuit is actually implemented [IEEE Symposium on VLSI Circuits (May)], however, N=100 holds.
In the CMOS process, the progress of finer patterning has resulted in MOS transistors of very small size. By contrast, the size of diodes that employ parasitic bipolar elements is greater than that of MOS transistors by an order of magnitude.
Further, since the ratio N between the diodes D1 and D2 in FIG. 7 is enlarged from one to two digits, the area on the chip is enlarged. [Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-11-45125